It has been a recent trend in dynamic random access memory (DRAM) to increase the density of DRAM circuits. However, as higher density DRAM cells are developed, the area available for capacitors that are used in the DRAM cells decreases. Simply put, the amount of space allotted for a single DRAM cell is becoming smaller and smaller. Several effects arise from this condition. First, in order to achieve desired performance, the capacitance of the capacitor for each DRAM cell must be maintained as large as possible. One common way of achieving this goal is to increase the capacitor node height. The large height of the capacitor node increases the depth of subsequent metal contacts, resulting in a large amount of substrate silicon loss and field oxide damage during the step of etching through the oxide to form the metal contact hole or via.
Another effect is the increase in difficulty in obtaining an acceptable photolithographic pattern. As device dimensions shrink, it is often necessary to use a bottom anti-reflective coating (BARC) to better define the photolithographic pattern. The use of the BARC increases the cost of the process as well as interfering with other process steps, such as opening a landing pad area in the DRAM cell.
The present invention provides a process for simultaneously forming DRAM landing pads, borderless metal contacts, bit line contacts, self-aligned node contacts and capacitor node contacts using silicon oxynitride.